The invention is related in general to memory devices. In particular, the invention is related to memory devices capable of operating in a burst access mode, wherein sequential data can be transferred to and from the memory device at the rate of one word per clock cycle.
Advances in the art of microprocessor technology have led to the development of so-called "burst mode" devices in order to increase overall system performance. Burst mode devices, for example the AMD 29000 RISC processor and the Motorola 68030, are processors capable of supporting a burst mode memory read or write operation, wherein sequential data words are transferred to and from a memory device without requiring the processor to provide a read or write address for each data word. More specifically, the processor need only supply a single starting address to the memory device in a burst access mode. Thereafter, the address count is incremented by the memory device in order to sequentially write to or read from a plurality of address locations within the memory device. Higher system performance can therefore be attained as the processor is not required to provide the address location for each data word to be transferred.
In addition to operating in a burst access mode, it is desirable that the memory device be randomly accessible so that data can be stored at and retrieved from nonsequential address locations, preferably at the same time a burst access mode operation is being performed. The two modes of operation can be accommodated simultaneously if a dual-port memory device is provided, i.e., a dual-port RAM capable of performing a random access read or write operation on one port while simultaneously reading or writing sequential data in a burst mode on a second port.
Implementation of a burst access memory (hereinafter BAM) capable of both random access and burst mode operation as described above could possibly be accomplished with current state of the art dual-port RAMs. Dual-port RAMs, however, have disadvantages which limit their applicability to a commercially viable BAM. For example, dual-port RAMs are more expensive, more difficult to manufacture, and have lower densities as compared to single-port RAMs. Current single port RAM cells are half the size of current dual-port RAM cells, and current single-port memory array densities are generally a generation ahead (4.times.density) of current dual-port memory arrays. As it is unlikely that future advances in dual-port technology will ever eclipse advances in single-port technology, single-port memory arrays will most likely always maintain the advantages over dual-port memory arrays listed above.
Accordingly, it would be desirable to provide a BAM having the advantages of a single-port memory array described above that could operate in both a burst access mode and a random access mode simultaneously. In addition, it would be desirable to provide a BAM that could provide both burst access mode and random access mode at high operating speeds (on the order of 50 MHz) to support high speed processors such as the AMD 29000 at 33 MIPs.